There are three built-in design-rule checkers: incremental, hierarchical, and schematic.

The incremental design-rule checker is always running, examining your layout, and issuing error messages when an error is detected. It checks only the current cell, and does not consider the contents of cell instances, lower in the hierarchy. It therefore offers an instant analysis, but not a complete one.

The hierarchical design-rule checker uses the same rules and techniques as the incremental checker, but it checks all levels of hierarchy below the current cell. To run it, use the Check Hierarchically command (in menu Tools / DRC). To check only a selected subset of the current cell, use Check Selection Hierarchically.

The schematic design-rule checker looks for issues that make drawing or editing of the cell difficult. These are the errors that is finds:

  1. Nodes:
  2. Arcs:

After analysis of the circuit, you can review the errors by typing ">" and "<" to step to the next and previous error that was found. You can also see a list of errors in the cell explorer (see Section 4-5-2).